发明名称 |
Method for optimizing decoupling capacitor design in delay locked loops |
摘要 |
A method for optimizing decoupling capacitance in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and an amount of the decoupling capacitance is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing decoupling capacitance in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize decoupling capacitance in a delay locked loop is provided.
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申请公布号 |
US2003154065(A1) |
申请公布日期 |
2003.08.14 |
申请号 |
US20020075783 |
申请日期 |
2002.02.14 |
申请人 |
GAUTHIER CLAUDE;AMICK BRIAN;LIU DEAN;TRIVEDI PRADEEP |
发明人 |
GAUTHIER CLAUDE;AMICK BRIAN;LIU DEAN;TRIVEDI PRADEEP |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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