NAND flash memory device has registers for serially receiving address, command and output data of input buffer circuits based on respective lead signals from a control logic

摘要

An address register (150) receives address of an output signal of an input buffer circuit (160) based on an address load signal from a control logic (200). A command register receives a command output from the buffer circuit based on a command load signal from control logic. A data input register (190) receives simultaneously the outputs of buffer circuits (160,170) based on data load signal from the control logic. An independent claim is also included for non volatile memory operating method.