| 摘要 |
The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital data input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).
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