发明名称 |
Method for fabricating a memory cell |
摘要 |
An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .
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申请公布号 |
US2003151091(A1) |
申请公布日期 |
2003.08.14 |
申请号 |
US20030378101 |
申请日期 |
2003.02.28 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
PALM HERBERT;WILLER JOSEF |
分类号 |
H01L21/8247;H01L21/336;H01L21/8246;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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