| 摘要 |
There is provided a micro-processor including (a) a pre-fetch cue FIFO which fetches and stores therein a command code, (b) a pre-fetch cue valid indicating that an effective command code is stored in the pre-fetch cue FIFO, (c) an access priority judging circuit receiving a pre-fetch request signal indicating that there is vacancy in the pre-fetch cue FIFO, a cue empty signal indicating that the pre-fetch cue FIFO is entirely empty, and an operand data request signal indicating that there has been generated an operand data access, and determining a kind of next bus access, (d) a bus state control circuit transmitting a bus interface signal, based on the kind of next bus access having been determined by the access priority judging circuit, and also transmitting a burst transfer signal indicating that a memory is in a condition for carrying out burst transfer, and (e) an access register storing data about the previous bus access. The access priority judging circuit takes a command fetch access in preference to an operand data access in the next bus access when data stored in the access register is a command fetch access, and the pre-fetch request signal, the operand data request signal, and the burst transfer signal are all transmitted.
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