| 摘要 |
A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal. |
