| 摘要 |
Systems and methods for programmable logic arrays having depletion mode, non volatile p-channel floating gate transistors with ultra thin tunnel oxides are provided. The programmable logic arrays of the present invention can be programmed with voltages of 2.0 to 3.0 Volts and the normal operating voltages on the control gates are of the order 1.0 Volt. The depletion mode, non volatile p-channel floating gate transistors the present invention, include a range of floating gate potentials over which charge can not leak on to or off of the floating gate. The non volatile p-channel floating gate transistors in the programmable logic array include an oxide layer of less than 50 Angstroms (Å) which separates the floating gate from a p-type doped channel region separating a source and a drain region in a substrate.
|
