发明名称 Integrated circuit device including a layered superlattice material with an interface buffer layer
摘要 An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.
申请公布号 US6605477(B2) 申请公布日期 2003.08.12
申请号 US20020262003 申请日期 2002.09.30
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO, LTD. 发明人 UCHIYAMA KIYOSHI
分类号 H01L21/02;H01L21/316;H01L21/8246;H01L27/105;(IPC1-7):H01L21/00 主分类号 H01L21/02
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