发明名称 |
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit |
摘要 |
An apparatus for concurrently executing controller single instruction single data (SISD) instructions and single instruction multiple data (SIMD) processing element instructions comprising a combined controller and processing element. At least first and second simplex instructions each comprise a mode of operation bit, said mode of operation bit in the first simplex instruction specifying a controller SISD operation for execution by the controller, and the mode of operation bit in the second simplex instruction specifying a procesing element SIMD operation for execution by the processsing element. A very long instruction word (VLIW) contains said at least first and second simplex instructions.
|
申请公布号 |
US6606699(B2) |
申请公布日期 |
2003.08.12 |
申请号 |
US20010783156 |
申请日期 |
2001.02.14 |
申请人 |
BOPS, INC. |
发明人 |
PECHANEK GERALD G.;REVILLA JUAN G. |
分类号 |
G06F15/16;G06F9/30;G06F9/318;G06F15/173;G06F15/80;(IPC1-7):G06F15/80 |
主分类号 |
G06F15/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|