发明名称
摘要 PROBLEM TO BE SOLVED: To monitor a RAKE composing and a delay profile surely and easily obtaining correlation values generated in a plurality of paths through multipath arrival and information on chip delay behind reference receiving timing without increasing the circuit scale. SOLUTION: Received spread data are inputted and delayed by a reception delay means 101. A spread code is delayed by a shift register 102 and latched by a latch circuit 103. A multiplying means 104 multiplies the outputs of individual stages of reception delay means 101 and latch circuits 103, an adding means 105 finds the sum of the individual multiplication results, and then an absolute value calculating means 106 obtains the correlation absolute value. Then the correlation absolute value is inputted as an address of a memory means 108 and a fixed value (or chip delay value) is inputted and written as data. Then the higher-order to lower-order addresses of the memory means 108 are read out in this order to output correlation measured values (and chip delay value) in the order from a minimum to a maximum value.
申请公布号 JP3435368(B2) 申请公布日期 2003.08.11
申请号 JP19990110522 申请日期 1999.04.19
申请人 发明人
分类号 H03H17/00;H04B1/10;H04B1/707;H04B1/7093;H04B1/711 主分类号 H03H17/00
代理机构 代理人
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