| 摘要 |
PURPOSE:To reduce the number of step of an addition, to shorten arithmetic time and to reduce logical amount to be processed with respect to a multiplier circuit which is suitable to be mounted, on a DSP, etc., developed for speedily executing the calculations, etc., required for a graphic processing. CONSTITUTION:When the multiplication of a number X to be multiplied of 2n bits and a number X of 2n bits is performed, the number X to be multiplied is divided into x1 of upper n bits and x0 of low-order n bits and a multiplication Y is divided into y1 of the upper n bits and y0 of the low-order n bits. Multiplications x1Xy0, x1Xy1 and x0Xy1 are performed by first, second, third and fourth corrected 2-bit both method respectively. The multiplication results z1, z2, z3 and z4 of the multiplications x1Xy0, x0Xy0, x1Xy1 are added upper a prescribed rule. |
