发明名称 |
COMPRESSION METHOD FOR INTEGRATED CIRCUIT MODEL |
摘要 |
PROBLEM TO BE SOLVED: To mitigate the necessity of a memory for an IC analysis work by substantially reducing the size of a net list. SOLUTION: A compression method 10 for an integrated circuit model is provided with a step 12 selecting a first net from a plurality of nets included in a distributed integrated circuit model and a step compressing a second net by removing the total resistance from a second net 54 to be connected to the first net and adding the whole capacitor of the second net. The steps can simplify the size and the complexity of the integrated circuit model while retain information on the second net required for the analysis. COPYRIGHT: (C)2003,JPO
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申请公布号 |
JP2003223478(A) |
申请公布日期 |
2003.08.08 |
申请号 |
JP20020342700 |
申请日期 |
2002.11.26 |
申请人 |
HEWLETT PACKARD CO <HP> |
发明人 |
KELLER S BRANDON;ROGERS GREGORY DENNIS |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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