发明名称 HARDWARE ACCELERATION SYSTEM FOR FUNCTION SIMULATION
摘要 PROBLEM TO BE SOLVED: To provide a hardware acceleration system materializing a low cost, a high performance, a low turnaround time, and a high scalability. SOLUTION: This hardware acceleration system for the function simulation is provided with a general circuit board having a logic chip and a memory. The circuit board can be connected to a computing device by a plug. This system is so applied that the computing device guides DMA (direct memory access) transfer between memories related to the circuit board and the computing device. The circuit board can be constituted using a simulation processor. The simulation processor can be programmed for, at least, a circuit design. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003223476(A) 申请公布日期 2003.08.08
申请号 JP20020334637 申请日期 2002.11.19
申请人 NEC CORP 发明人 CADAMBI SRIHARI;ASHAR PRANAV
分类号 G06F9/455;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F9/455
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