| 摘要 |
PROBLEM TO BE SOLVED: To shorten the time required for a circuit design by checking nonconformity of a logic design in an early stage and reducing the design manhour. SOLUTION: This circuit design device is provided with a gate step calculation part 11 allocating a unit delay value to all the cells of design objects after the logic design by a logic design part 1, allowing a delay value calculation part to calculate the maximum value or the minimum value of an integrating delay value while allowing a pass trace part 4A to trace a pass for the logic design result of the logic design part 1 with its allocating zero to all the nets between mutual cells as the delay value, and calculating the number of gate steps between order circuit cells in the design object circuit or between input output pins and the order circuit cells based on the maximum value or the minimum value of the integrating delay value. COPYRIGHT: (C)2003,JPO
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