| 摘要 |
PURPOSE: A process controlling method is provided to realize signal processing at a high speed with a low cost installed at a PC. CONSTITUTION: The signal processing accelerator includes plural same data processing units(10). Each data processing unit is connected to each other, and is connected to a host memory bus(30). Each data processing unit includes a signal processing processor(11), a commend cache(12), a data RAM(13), link controllers(14, 15), a main cache(16), a link cache(17), a DRAM(18), and a DRAM controller(19). A signal processor(25) comprises the signal processing processor(11), the main cache(16), and the data RAM(13). The link controllers(14, 15) comprise the main cache(13), and the link cache(17). When an access is a predetermined access, a memory area is allocated for communication between the host processor and a client processor. When the access is a common access, the common memory access is performed to the main memory.
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