发明名称 |
METHOD OF FORMING SMALL TRANSISTOR GATES BY USING SELF-ALIGNED REVERSE SPACER AS A HARD MASK |
摘要 |
A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.
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申请公布号 |
US2003148617(A1) |
申请公布日期 |
2003.08.07 |
申请号 |
US20020068053 |
申请日期 |
2002.02.05 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
ANG CHEW-HOE;LIM ENG-HUA;CHA RANDALL;ZHENG JIA-ZHEN;QUEK ELGIN;ZHOU MEI-SHENG;YEN DANIEL |
分类号 |
H01L21/28;(IPC1-7):H01L21/311 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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