发明名称 Extendible asynchronous and synchronous interface bus for broadband access
摘要 Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the methods of the invention, data is transferred on the bus in a repeating frame having a plurality of slots, each slot being defined as one bus clock cycle. Each slot may contain a synchronous or asynchronous data signal and one or more of the control lines are asserted during the slot time of the data to indicate the type of data. Two embodiments are provided. One utilizes a 25 MHz clock bus and a repeating frame of three hundred thirty-six slots. The other utilizes a 75 MHz clock bus and a repeating frame of one thousand eight slots.
申请公布号 US2003147416(A1) 申请公布日期 2003.08.07
申请号 US20020072329 申请日期 2002.02.06
申请人 TRANSWITCH CORPORATION 发明人 GILSDORF JOHN F.;YANG YUNG-YUAN
分类号 H04L12/64;(IPC1-7):H04L12/403 主分类号 H04L12/64
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