| 摘要 |
The present invention relates to the management of caches in a data processing apparatus. An "n'-way set-associative cache is disclosed, each way comprises a plurality of cache lines, each of said plurality of cache lines comprising a plurality of data words, each of said plurality of data words having associated therewith a unique address. The unique address includes an address portion. The "n'-way set-associative cache comprises a cache memory comprising "n' memory units, each of the "n' memory units having a plurality of entries, respective entries in each of the "n' memory units being associated with the same address portion and being operable to store a data word having that same address portion within its unique address. Also provided is a cache controller operable to determine for a particular way into which of the entries to store the data words of a cache line, each data word being stored at one of the entries within one of the "n' memory units associated with that data word's address portion, each subsequent data word of the cache line being stored in a different memory unit to the previous data word of the cache line so as to maximise the distribution of the data words across the "n' memory units. By maximising the distribution of the cache line data words across the memory units, the number of data words that can be accessed each cycle can be increased. Hence, for any cache line, the number of cycles required to access that cache line is accordingly decreased.
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