TRANSCEIVER USING A HARMONIC REJECTION MIXER

摘要

A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a switchable signal responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration while the output offset phase-locked loop reduces the power consumption. TheThe switchability of the filter allows the utilisation of the transceiver for EGSM, DCS and PCS communication. The local oscillator may use a integer or fractional-N phase-locked loop.