| 摘要 |
The add compare select module has a mechanism providing comparison selection. There is a first adder (12,14) adding a metric state (MT1) and an adjustment of a preceding value (SI1) producing a first metric state and a second adder (16,18) adding a metric state (MI2) and a preceding value (SI2). A coupler (20) selects the higher of the two resultant states, and a memory (MO) stores the information. A mechanism (22,24,26,27,28) determines the adjustment value of the metric state (SO) carrying a single bit. A second memory (29) memorises the adjustment state.
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