发明名称 |
Device for recognising clock failure |
摘要 |
The arrangement for detection of a clock signal failure comprises: a counter (CNT1) that counts the number of pulses of the clock signal (CLK) between two defined events; an arrangement for monitoring if the count exceeds a reference value one or more; whereby the detected events are provided by components connected to other components that send signals (BUSSIG) to each other over a connection bus. |
申请公布号 |
EP1333579(A1) |
申请公布日期 |
2003.08.06 |
申请号 |
EP20020002305 |
申请日期 |
2002.01.30 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
VON WENDORFF, WILHARD CHRISTOPHORUS, DR. |
分类号 |
H03K5/19 |
主分类号 |
H03K5/19 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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