| 摘要 |
A digital-to-analog converter includes a signal generator, a low-weighted value manager, and a voltage smoothing circuit. The signal generator performs a pulse width modulation based on a reference clock signal and upper nh bits of the n-bit digital data to generate a first pulse-width-modulated signal having first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data and a pwm cycle signal. The low-weighted value manager divides a pulse width in response to a value of the lower nl bits of the n-bit digital data into fraction pulse widths, to respectively add the fraction pulse widths to the first pulses, and to generate a second pulse-width-modulated signal having second pulses having the first pulse width and one of the fraction pulse widths. <IMAGE> |
