| 摘要 |
Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an equalize circuit to equalize a pair of internal nodes to a prescribed potential, a transfer gate circuit activated, when the equalize circuit completes equalization, to couple the pair of first signal lines and the pair of internal nodes, an amplifier circuit to differentially amplify the signals on the internal nodes when the transfer gate completes the transfer operation, an output transfer circuit to transmit the signals on the pair of internal nodes onto the pair of second signal lines in synchronization with the clock signal, and a control circuit to control the operation of the equalize circuit, the transfer gate circuit and the amplifier circuit. After the pair of internal nodes is equalized to the prescribed potential, the signals from the pair of first signal lines are received and amplified. Even if the signals are small amplitude signals, therefore, they can be correctly amplified and transferred in synchronization with the clock signal without destroying the signal amplitude.
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