Hardware implementation of a decimating finite impulse response filter

摘要

The invention provides apparatus and methods for generating the coefficients of a finite impulse response digital filter used in signal sample rate conversion. Sequence generation circuitry provides a discrete-time sequence x(n) that is coupled to a plurality of cascaded discrete-time integrators that generate the filter coefficients h(n). Bit serial and interleaved bit serial implementations are described that provide efficient coefficient generators. The described apparatus and methods also may be used to efficiently implement a finite impulse response digital filter for an oversampling analog-to-digital converter.