发明名称 Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages
摘要 A single tier cavity down integrated circuit package having a die with outer bond pads and staggered inner bond pads is described. The bond pads of the die are assigned to associated supply rings and bond fingers of the package according to a design methodology where in one embodiment at least all bond pads connected to the supply rings are outer bond pads, and staggered inner bond pads are connected to bond fingers. There is further described a method for assigning bond pads of the die to associated supply rings and bond fingers of the package, as well as, a die having staggered bond pads formed in accordance with the method of the present invention.
申请公布号 US6603199(B1) 申请公布日期 2003.08.05
申请号 US20000724739 申请日期 2000.11.28
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 PODDAR ANINDYA
分类号 H01L23/498;(IPC1-7):H01L23/52 主分类号 H01L23/498
代理机构 代理人
主权项
地址
您可能感兴趣的专利