| 摘要 |
A processor has an instruction decoder including a register number translation unit for translating a register number specified by an instruction into the number of a physical register to be actually used in execution of the instruction. In an operation to decode an instruction, after a register number specified by the instruction is translated into the number of a physical register to be actually used in execution of the instruction, a register rename unit replaces the number of the physical register with the number of a rename register. As a result, the translation of a register number specified by the instruction into the number of a physical register to be actually used in execution of the instruction can be changed dynamically at run time even for a superscalar processor carrying out register renaming operations.
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