发明名称 |
Semiconductor integrated circuit device including dummy patterns located to reduce dishing |
摘要 |
A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer. |
申请公布号 |
US6603162(B1) |
申请公布日期 |
2003.08.05 |
申请号 |
US20000692450 |
申请日期 |
2000.10.20 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
UCHIYAMA HIROYUKI;CHAKIHARA HIRAKU;ICHISE TERUHISA;KAMINAGA MICHIMOTO |
分类号 |
H01L21/76;H01L21/302;H01L21/304;H01L21/3105;H01L21/3205;H01L21/762;H01L21/768;H01L23/52;H01L23/544;(IPC1-7):H01L27/108;H01L29/76;H01L31/119;H01L23/48 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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