| 摘要 |
A high order SINC interpolator and as a high order SINC decimator. The high order SINC interpolator includes an interpolator input and a plurality of cascades of integrators. The inputs of each of the cascades are coupled to the interpolator input through a low frequency delay circuit. The outputs of each of the cascades of integrators are coupled through a plurality of adders to generate a single interpolator output. The high order SINC decimator includes a decimator input and a plurality of cascades of integrators. The decimator input is coupled to the input of each of the cascades of the integrators. At least one low frequency delay circuit is coupled to an output of the cascades of the integrators and the output of each low frequency delay circuit is coupled to the decimator output through an adder.
|
