METHOD FOR FABRICATING EMBEDDED MEMORY DEVICE WITH FLAT CELL STRUCTURE

摘要

PURPOSE: A method for fabricating an embedded memory device with a flat cell structure is provided to decrease surface resistance of a logic circuit region by forming a silicide preventing layer only between gate electrodes in a flat cell array region and by performing a salicide formation process on the flat cell array region and the logic circuit region. CONSTITUTION: A BN+ diffusion region is formed in a semiconductor substrate(100) in the flat cell array region. A gate insulation layer(110) and a gate electrode(120') are formed on the semiconductor substrate in the flat cell array region and the logic circuit region. A source/drain junction is formed in the semiconductor substrate in the logic circuit region. A spacer is formed on the sidewall of the gate electrode in the flat cell array region and the logic circuit region. The silicide preventing layer(124) is formed in a portion except the gate electrode in the flat cell array region. A silicide process is performed on the flat cell array region and the logic circuit region to form a silicide layer(126') on the gate electrode in the flat cell array region while a silicide layer is formed on the gate electrode and the source/drain junction in the logic circuit region.