发明名称 INTERNAL VOLTAGE LEVEL CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND THEIR CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a voltage level control circuit whose power consumption is reduced, and to provide a control method. SOLUTION: When an external signal PL becomes 'H', an output signal La of a latch 11 becomes the 'H', N.FETs 14, 17, 24 are turned on. Thereby, the circuit becomes an active state, and the 'H' is outputted as a signal A for controlling boost-voltage Vbt (word line drive voltage). When the boost- voltage Vbt is boosted and arrives at reference voltage Vref2, voltage V2 is made 'H', thereby, the signal A is made 'L'. When the signal A becomes 'L', the latch 11 becomes a through state. Since the signal PL is the 'L' at the time, the output signal La of the latch 11 becomes the 'L', the N.FETs 14, 17, 24 are turned off. Thus, power consumption is reduducet by turning off the N.FETs 14, 17, 24 in a time zone being not required. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003217284(A) 申请公布日期 2003.07.31
申请号 JP20030006320 申请日期 2003.01.14
申请人 NEC CORP 发明人 TAKAHASHI HIROYUKI;NAKAGAWA ATSUSHI
分类号 H01L27/04;G11C11/403;G11C11/407;G11C11/408;H01L21/822;(IPC1-7):G11C11/408 主分类号 H01L27/04
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