| 摘要 |
PROBLEM TO BE SOLVED: To provide a condition selective adder for a digital signal processor capable of reducing a current consumption and a delay time by improving the operation speed and to provide its method. SOLUTION: This condition selective adder is provided with a carry production part producing a carry of two input data X0-Xn-1 and Y0-Yn-1 composed of n bit and a sum production part producing the sum of the input data. The carry production part is provided with a first input part for operating the carry of the input data by taking account of the initial carry and receiving the input of the data based on input data Xi and Yi, a second input part for receiving the input of the initial carry, and a selection part receiving the input of an exclusive logical sum of the input data Xi and Yi, and includes, at least, one or more sub-carry production parts outputting either one of the data based on the input data Xi and Yi inputted in the first input part by the exclusive logic sum value to be inputted in the selective part or the initial carry inputted in the second input part. The sum production part operates the sum using the carry produced in the carry production part so as to reduce the power consumption, a chip area, logic use, and the delay time. COPYRIGHT: (C)2003,JPO
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