| 摘要 |
<P>PROBLEM TO BE SOLVED: To perform easily and under less constraint the timing design of an input-output signal for preventing the occurrence of a timing error in data transfer between a plurality of LSIs. <P>SOLUTION: A semiconductor integrated circuit 10 is provided with: a clock delay information detection circuit 6 for outputting optimum delay information according to the phase difference between an input clock EXP-CLK from the LSI of a preceding stage and a reference clock CLK; a clock selection circuit 5 for supplying a clock selected on the basis of the delay information outputted from the clock delay information detection circuit 6 to an F/F group 1; and a clock distribution circuit 7 for supplying the reference clock CLK to an F/F group 2. An optimum clock among a plurality of clocks obtained by delaying the reference clock CLK with various amounts of delay different from one another is supplied to the F/F group 1 just after an input pin in accordance with the amount of delay to the reference clock CLK of the clock EXP-CLK inputted from the LSI of the preceding stage. <P>COPYRIGHT: (C)2003,JPO |
