| 摘要 |
<p>A decoder and decoding method that incorporates an improved Chien search cell (1100), in which memory requirements and delay are both reduced. The prior art Chien search cell processes the error location polynomial coefficient in an iterative manner, beginning with an alpha exponent of ‘0’ which is decremented with each clock cycle until the exponent decreases to a value of -j(N-1). In the improved Chien search cell (1100), the value of the alpha exponent begins at a value of -j(N-1)and is incremented with each clock cycle until the exponent reaches 0. Therefore, during the first clock cycle, the polynomial coefficient (1100) is multiplied by a premultiplier (1150), forwarded to a multiplexer (1120), and routed to a register (1130) for storage. On Subsequent clock cycles, the output of the register (1130) is forwarded to another multiplier (1140) and then routed by the multiplexer (1120) back to the register (1130).</p> |
