| 摘要 |
An n-type impurity (ions) is implanted into a cell P-well 104 through contact holes 161 to form n-type diffusion layers 171. At this time, the ranges over which no n-type impurity diffusion zone 171 is to be formed are all covered by a third silicon oxide film 151 and, as a result, no n-type impurity is implanted over these ranges. In addition, since the contact holes 161 are formed between transfer gates 111 through self-alignment, the n-type impurity diffusion zones 171 are formed at specific positions with a high degree of accuracy even in a highly miniaturized DRAM. Furthermore, since the transfer gates 111 are each provided with a side wall 115 constituted of a silicon nitride stopper film 123 and a second silicon oxide film 121, the n-type impurity is not implanted into the transfer gates. Thus, a manufacturing method that makes it possible to manufacture a semiconductor device achieving outstanding data retention characteristics and capable of sustaining a specific threshold voltage level while minimizing the increase in the production costs is provided.
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