发明名称 |
Integrated circuit analysis method and program product |
摘要 |
A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
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申请公布号 |
US2003145298(A1) |
申请公布日期 |
2003.07.31 |
申请号 |
US20020059486 |
申请日期 |
2002.01.29 |
申请人 |
PIE CHARLES COREY;RANSON GREGORY LOUIS |
发明人 |
PIE CHARLES COREY;RANSON GREGORY LOUIS |
分类号 |
G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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