| 摘要 |
PROBLEM TO BE SOLVED: To provide the technology which enables to reduce a cell area of a non-volatile memory which uses a non-conductive electric charge trap film as an electric charge accumulation region. SOLUTION: First patterns P1 for defining source and bit lines are arranged in the stripe geometry at a pitch twice as large as the minimum processing size F. Second patterns P2 for defining a first control gate and third patterns P3 for defining a second control gate are arranged alternately in the stripe geometry perpendicularly to the first patterns P1 at a pitch twice as large as the minimum processing size F. The second patterns P2 and the third patterns P3 are constituted of different layers, with part of the third patterns overlapping the second patterns P2. COPYRIGHT: (C)2003,JPO
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