| 摘要 |
Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval. The apparatus includes a predictor, which determines, for each of the symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, and logic, which compares the expected value with the at least one bit of each of the second symbols in the FIFO, so as to determine a relative skew between the first and at least the second channel.
|
