发明名称 |
Reduction of negative bias temperature instability in narrow width PMOS using F2 implanation |
摘要 |
In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of F2 side wall implantation, comprising: a) forming a shallow trench isolation (STI) region in a substrate; b) forming a gate on a gate oxide in the substrate; c) forming a liner layer in said shallow trench isolation region and subjecting the liner layer to oxidation to form a STI liner oxidation layer; d) implanting F2 into side walls of said STI liner oxidation layer at a large tilted angle in sufficient amounts to affect reduction of negative bias temperature instability after a high density plasma fill of the STI F2 implanted liner oxidation layer; and e) filling the STI F2 implanted structure from step c) with a high density plasma (HDP) fill to affect reduction of negative bias temperature instability.
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申请公布号 |
US2003143812(A1) |
申请公布日期 |
2003.07.31 |
申请号 |
US20020059321 |
申请日期 |
2002.01.31 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
LIN CHUAN |
分类号 |
H01L21/265;H01L21/762;H01L21/8234;H01L29/10;(IPC1-7):H01L21/336;H01L21/425;H01L21/76 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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