发明名称 |
Logical circuit and semiconductor device |
摘要 |
The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current. |
申请公布号 |
US2003141905(A1) |
申请公布日期 |
2003.07.31 |
申请号 |
US20030345242 |
申请日期 |
2003.01.16 |
申请人 |
HITACHI, LTD. AND HITACHI ULSI SYSTEMS CO.,LTD. |
发明人 |
SAITOU YOSHIKAZU;OSADA KENICHI |
分类号 |
H01L21/822;H01L27/04;H03K19/00;H03K19/0948;(IPC1-7):H03K19/094 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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