发明名称 |
Semiconductor memory device capable of performing high-frequency wafer test operation |
摘要 |
A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.
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申请公布号 |
US2003142566(A1) |
申请公布日期 |
2003.07.31 |
申请号 |
US20030352163 |
申请日期 |
2003.01.28 |
申请人 |
SOHN KWON-IL;CHO UK-RAE;LEE KWANG-JIN |
发明人 |
SOHN KWON-IL;CHO UK-RAE;LEE KWANG-JIN |
分类号 |
G01R31/28;G11C11/413;G11C29/00;G11C29/06;G11C29/14;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G01R31/28 |
代理机构 |
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