| 摘要 |
PURPOSE: A DRAM refresh controller by using an improved pulse generator is provided to implement the refresh operation at a minimum time interval by configuring the DRAM refresh controller with matching to tRAS and tRP required for the minimum. CONSTITUTION: A DRAM refresh controller by using an improved pulse generator(41) includes an inverter(INV0), a first NAND gate(NAND1), a second NAND gate(NAND2), a third NAND gate(NAND3), a time delay circuit(42a) and a plurality of time delay circuits(42a,42b,42c). In the DRAM refresh controller, the invertor(INV0) inverts the refresh signal and the first NAND gate(NAND1) outputs the row active signal(row_act) by NAND operating the inverted refresh signal(refb) and the feedback pulse signal(pulse_b). In the improved pulse generator(41), the plurality of time delay circuits(42a,42b,42c) configured by sequentially connecting to each other with a different delay time delay and output the row active signal(row_act) by the predetermined times(d1,d2,d3). The time interval maintaining the low level by the output signal(d123_b) of the third NAND gate(NAND3) and the time interval maintaining the high level by the pulse signal(pulse_b) are determined by the first delay signal(d1).
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