发明名称 A SERIAL TO PARALLEL AND PARALLEL TO SERIAL DATA TRANSCEIVER
摘要 <p>A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.</p>
申请公布号 WO2003063369(A2) 申请公布日期 2003.07.31
申请号 US2003001613 申请日期 2003.01.17
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