发明名称 SYSTEM LSI VERIFYING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To propose a command syntax conforming to verification evaluation of a system LSI and carry out efficient verification evaluation from one command to an evaluation object in a verification evaluation target in regard to a system LSI verifying system of an interpreter system. <P>SOLUTION: In a script 30 for evaluating a verification evaluation target part 50, the evaluation object in the evaluation target is specified by a pinpoint, region, a minimum value, a maximum value and a boundary value. An evaluation program is automatically generated by a program generating part 40 from the script. The generated evaluation program is executed by a program executing part 21. An interruption process is executed with respect to an interruption input generated by the verification evaluation target part 50 at optional timing. An execution result of the evaluation program is determined by a program determining part 22 on the basis of output data from the verification evaluation target or execution information of the interruption process. Determined verification result information is stored in a verification result memory unit 60. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003216452(A) 申请公布日期 2003.07.31
申请号 JP20020008752 申请日期 2002.01.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHINOZAKI MITSUNORI;OCHIAI NARIYUKI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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