| 摘要 |
<p>A periodic controlled realignment of the ring oscillator VCO (18) in a phase locked loop (10) is used to effect phase correction in a CMOS phase locked loop. A realignment to a buffered version of the reference signal is conducted periodically, at a time when an edge of the VCO waveform would ideally coincide with an edge in the reference signal. A preferred embodiment CMOS phase locked loop (10) of the invention uses a ring oscillator voltage controlled oscillator (18). A divide by M circuit (20) is driven by an output of the voltage controlled oscillator. A control voltage circuit accepts a reference signal and a signal from the divide by M circuit, and produces a control voltage proportional to a phase difference between the output of the voltage controlled oscillator and the reference signal to control the voltage controlled oscillator. A realignment circuit (14, 16) responsive to the reference signal provides realignment signal into the voltage controlled oscillator when an edge in the waveform of the voltage controlled oscillator ideally coincides with an edge of the reference signal.</p> |
