发明名称 ESD protection circuit with controlled breakdown voltage
摘要 An ESD protection circuit utilizes a trigger network to allow the user to select the breakdown voltage of an avalanche transistor. By implementing the trigger network as a string of diodes coupled between the collector and base of the avalanche transistor, the trigger voltage can be programmed between BVCEO and BVCBO by adjusting the number of diodes. When the voltage across the trigger network reaches a predetermined value at which the diodes are conducting under forward biased conditions, but the transistor is below BVCBO, base charge supplied to the transistor caused the transistor to avalanche. A base-emitter resistor prevents false triggering by removing leakage charge from the base of the transistor, and another resistor coupled in series with the base of the transistor limits the removal of charge, thereby causing the avalanche to be self-sustaining once initiated by the trigger network. One or more forward-biased diodes can be coupled in series with the transistor to increase the voltage across the protection circuit during avalanche. In an alternative embodiment, one or more diodes are connected in series with an open-base avalanche transistor for increasing the voltage across the protection circuit when the transistor avalanches, thereby increasing the margin between the avalanche voltage and the normal operating voltage.
申请公布号 US6600356(B1) 申请公布日期 2003.07.29
申请号 US19990302562 申请日期 1999.04.30
申请人 ANALOG DEVICES, INC. 发明人 WEISS FREDERICK G.
分类号 H01L27/02;H03K5/08;(IPC1-7):H03K5/08 主分类号 H01L27/02
代理机构 代理人
主权项
地址