发明名称 Method for improving integrated circuits bonding firmness
摘要 A method for improving the integrated circuits bonding firmness, whose principle is that after the later film is piled on top of the previous film, the upper surface of the later film will be affected by the previous film. Among the metal layers of the multi-level interconnection, the metal layer under and most close to the bond pad metal (the top metal layer of the multi-level interconnection) has a regular or an irregular layout pattern, which is under the predetermined regions serving as bond pad windows. These regular or irregular layout patterns result in a rough upper surface, and then improves the firmness of bond wires.
申请公布号 US6599578(B2) 申请公布日期 2003.07.29
申请号 US20020224360 申请日期 2002.08.21
申请人 INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 发明人 PENG JENG-JIE;KER MING-DOU;WANG NIEN-MING
分类号 H01L23/485;(IPC1-7):B05D1/36 主分类号 H01L23/485
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