发明名称 Arrangements for independent queuing/tracking of transaction portions to reduce latency
摘要 Arrangements directed to arrangements for queuing/tracking of transaction portions to reduce latency are disclosed. A queue/pointer arrangement to queue first execution information portions and second execution information portions for transactions may comprise a first queue and a second queue. The first queue and the second queue may be adapted to store the first execution information portions and the second execution information portions, respectively, may have a first pointer arrangement and a second pointer arrangement, respectively, and may operate independently of one another. The first execution information portions and corresponding second execution information portions with respect to the first queue and the second queue, respectively may comprise, address portions and full-line portions for the transactions.
申请公布号 US6601117(B1) 申请公布日期 2003.07.29
申请号 US20000649171 申请日期 2000.08.29
申请人 INTEL CORPORATION 发明人 DAHLEN ERIC J.;OKI HIDETAKA
分类号 G06F3/00;G06F13/36;(IPC1-7):G06F3/00 主分类号 G06F3/00
代理机构 代理人
主权项
地址
您可能感兴趣的专利