发明名称 |
Method to partition the physical design of an integrated circuit for electrical simulation |
摘要 |
A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.
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申请公布号 |
US6601025(B1) |
申请公布日期 |
2003.07.29 |
申请号 |
US19990371202 |
申请日期 |
1999.08.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DITLOW GARY S.;DOOLING DARIA R.;MOORE RICHARD L.;MORAN DAVID E.;WILKINS THOMAS W.;WILLIAMS RALPH J. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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