发明名称 Quad pumped bus architecture and protocol
摘要 A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
申请公布号 US6601121(B2) 申请公布日期 2003.07.29
申请号 US20010925692 申请日期 2001.08.10
申请人 INTEL CORPORATION 发明人 SINGH GURBIR;GREINER ROBERT J.;PAWLOWSKI STEPHEN S.;HILL DAVID L.;PARKER DONALD D.
分类号 G06F13/36;G06F13/42;(IPC1-7):G06F13/00 主分类号 G06F13/36
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