发明名称 |
Semiconductor integrated circuit device |
摘要 |
A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.
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申请公布号 |
US6601218(B2) |
申请公布日期 |
2003.07.29 |
申请号 |
US20010803030 |
申请日期 |
2001.03.12 |
申请人 |
HITACHI, LTD. |
发明人 |
SATO MASAYUKI;UCHIYAMA KUNIO |
分类号 |
G01R31/28;G06F12/16;G06F17/50;G11C11/41;G11C11/413;G11C29/00;G11C29/02;G11C29/04;G11C29/12;H01L21/00;H01L21/336;H01L21/84;H01L27/04;H01L27/06;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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